4502 datasheet(10/214 Pages) RENESAS

10 / 214 page

4502 Group

REJ09B0193-0201

Rev.2.01

Feb 02, 2005

List of figures

CHAPTER 3 APPENDIX

Fig. 3.2.1 A/D conversion characteristics data ........................................................................ 3-25

Fig. 3.3.1 External 0 interrupt program example-1 ................................................................. 3-29

Fig. 3.3.2 External 0 interrupt program example-2 ................................................................. 3-30

Fig. 3.3.3 External 0 interrupt program example-3 ................................................................. 3-30

Fig. 3.3.4 Timer count start timing and count time when operation starts (T1, T2) ................ 3-31

Fig. 3.3.5 Analog input external circuit example-1 .................................................................. 3-32

Fig. 3.3.6 Analog input external circuit example-2 .................................................................. 3-32

Fig. 3.3.7 A/D converter operating mode program example .................................................. 3-32

Fig. 3.4.1 Selection of packages ............................................................................................... 3-36

Fig. 3.4.2 Wiring for the RESET input pin ............................................................................... 3-36

Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-37

Fig. 3.4.4 Wiring for CNVSS pin .................................................................................................. 3-37

Fig. 3.4.5 Wiring for the VPP pin of the built-in PROM version ............................................. 3-38

Fig. 3.4.6 Bypass capacitor across the VSS line and the VDD line ........................................ 3-38

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-39

Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-39

Fig. 3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-40

Fig. 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-40

Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-41

4502 Datasheet(PDF) 10 Page - Renesas Technology Corp