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SH7713 Datasheet(PDF) 564 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 564 Page - Renesas Technology Corp |
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564 / 904 page  Section 15 Realtime Clock (RTC) Rev.1.50 Aug. 30, 2006 Page 524 of 860 REJ09B0288-0150 15.3.18 RTC Control Register 3 (RCR3) RCR3 is a register that controls comparison of the BCD-coded year counter RYRCNT and the year alarm register RYRAR of the RTC. RCR3 is an 8-bit readable/writable register. Bit Bit Name Initial Value R/W Description 7 YAEN 0 R/W Year Alarm Enable When this bit is set to 1, comparison of the year alarm register (RYRAR) and the year counter (RYRCNT) is performed. From among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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