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SH7713 Datasheet(PDF) 593 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 593 Page - Renesas Technology Corp |
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593 / 904 page  Section 16 Serial Communication Interface with FIFO (SCIF) Rev.1.50 Aug. 30, 2006 Page 553 of 860 REJ09B0288-0150 16.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can be read or written to by the CPU at all times. SCBRR is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. The SCBRR setting is found from the following equation. Asynchronous mode: N = P φ 64 ×22n–1 × B × 106 – 1 Clock synchronous mode: N = P φ 8 × 22n–1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) P φ: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See table 16.2 for the relation between n and the clock.) Table 16.2 Relationship between n and Clock SCSMR Setting n Clock CKS1 CKS0 0 P φ 0 0 1 P φ/4 0 1 2 P φ/16 1 0 3 P φ/64 1 1 The bit rate error in asynchronous mode is found from the following equation: |
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