SH7713 datasheet(594/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 554 of 860

REJ09B0288-0150

Error (%) =

– 1

× 100

(N + 1)

× B × 64 × 22n–1

φ × 106













16.3.9

FIFO Control Register (SCFCR)

SCFCR performs data count resetting and trigger data number setting for the transmit and receive

FIFO registers, and also contains a loopback test enable bit.

SCFCR can be read or written to by the CPU at all times.

SCFCR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby

mode or in the module standby state, and retains its contents.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

RSTRG2

RSTRG1

RSTRG0

R/W

RTS Output Active Trigger 2 to 0

The

RTS signal goes high when the number of

receive data bytes in SCFRDR is equal to or greater

than the trigger set number shown in below.

RTS active trigger:

000: 15

001: 1

010: 4

011: 6

100: 8

101: 10

110: 12

111: 14

SH7713 Datasheet(PDF) 594 Page - Renesas Technology Corp

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