SH7713 datasheet(598/904 Pages) RENESAS

598 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 558 of 860

REJ09B0288-0150

16.3.11

Line Status Register (SCLSR)

SCLSR is a 16-bit register that indicates whether an overrun error occurs or not during reception.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

ORER

R/(W)*

Overrun Error

Indicates that an overrun error occurred during

reception and reception is ended abnormally.

0: Reception is in progress, or reception has

ended successfully*

[Clearing conditions]

• Power-on reset or manual reset

• When 0 is written to ORER after reading ORER

= 1

1: An overrun error occurred during reception*

[Setting condition]

When serial reception is completed while the

receive FIFO is full

Notes: 1. The ORER flag is not affected and

retains its previous state when the RE

bit in SCSCR is cleared to 0.

2. The receive data prior to the overrun

error is retained in SCFRDR, and the

data received subsequently is lost.

Serial reception cannot be continued

while the ORER flag is set to 1.

Note:

Only 0 can be written to clear the flag.

SH7713 Datasheet(PDF) 598 Page - Renesas Technology Corp

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