SH7713 datasheet(596/904 Pages) RENESAS

596 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 556 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

TFRST

R/W

Transmit FIFO Data Register Reset

Invalidates the transmit data in the transmit FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * A reset operation is performed in the event of

a power-on reset or manual reset.

RFRST

R/W

Receive FIFO Data Register Reset

Invalidates the receive data in the receive FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * A reset operation is performed in the event of

a power-on reset or manual reset.

LOOP

R/W

Loopback Test

Internally connects the transmit output pin (TxD) and

receive input pin (RxD), and

RTS pin and CTS pin,

enabling loopback testing.

0: Loopback test disabled

1: Loopback test enabled

16.3.10

FIFO Data Count Register (SCFDR)

SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and

SCFRDR.

Bits 12 to 8 show the number of transmit data bytes in SCFTDR, and bits 4 to 0 show the number

of receive data bytes in SCFRDR.

SCFDR can be read by the CPU at all times.

SCFDR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby

mode or in the module standby state, and retains its contents.

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