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SH7721 Datasheet(PDF) 855 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 855 Page - Renesas Technology Corp

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Section 24
USB Host Controller (USBH)
Rev. 3.00 Jan. 18, 2008 Page 793 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
17
PESC
0
R/W
Port Enable Status Change
This bit is set when the PES bit is cleared due to a
hardware event. This bit is not set by the change of writing
of HCD. Writing a 1 clears this bit. Writing a 0 has no
effect.
0: PortEnableStatus not changed
1: PortEnableStatus changed
16
CSC
0
R/W
Connect Status Change
This bit is set whenever the connection or disconnection
event occurs. Writing a 1 clears this bit. Writing a 0 has no
effect. If the CCS bit is cleared when SetPortReset,
SetPortEnable, or SetPortSuspend is written to, writing
when the power supply of the port is disconnected does
not occur, so this bit is set to enforce the driver to re-
evaluate the connection status.
0: CurrentConnectionStatus not changed
1: CurrentConnectionStatus changed
Note:
If the DR bit in USBHRDB is set, this bit is set only
after the root hub reset to inform that the system
that a device can be attached.
15 to 10
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.



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