SH7721 datasheet(1104/1524 Pages) RENESAS

1104 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1042 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

DATAEN 0

R/W

Data Enable

Starts write data transmission by a command with write data.

Resumes write data transmission when the transfer clock is

halted according to FIFO empty or one block writing is

terminated in multiblock write.

Write enable period: (1) after reception of a command

response with write data, (2) while transfer clock is halted

according to FIFO empty, (3) when one block writing in

multiblock write is terminated

Writes 0: Operation is not affected.

Writes 1: Starts or resumes transfer clock output and write

data transmission.

3 to 0

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

For write data transmission, the contents of the command response and data response should be

analyzed, and then transmission should be triggered. In addition, write data transmission should be

temporarily halted according to FIFO full/empty, and it should be resumed when the preparation

has been completed.

For multiblock transfer, the transfer clock output should be temporarily halted for every block

break to select either to continue to the next block or to abort the multiblock transfer command by

issuing the CMD12 command, and the transfer clock output should be resumed. To continue to the

next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command,

the CMDOFF bit should be set to 1 to abort the command sequence on the MMCIF side. Setting

RD_CONTI or DATAE bit between blocks, can be omitted when auto mode is used in pre-define

multi block transfer.

SH7721 Datasheet(PDF) 1104 Page - Renesas Technology Corp