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SH7721 Datasheet(PDF) 1108 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 1108 Page - Renesas Technology Corp

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Section 31
MultiMediaCard Interface (MMCIF)
Rev. 3.00 Jan. 18, 2008 Page 1046 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
3
DTBUSY
0
R
Data Busy
Indicates command execution status. Indicates that the
MMC is in the busy state during or after the command
sequence of a command without data transfer, which
includes the busy state in the response, or of a command
with write data has been ended.
0: Idle state waiting for a command, or command sequence
execution in progress.
1: MMC indicates data busy after command sequence ends.
2
DTBUSY_
TU
Undefined
R
Data Busy Pin State
Monitors level of the DAT pin and DO pin.
This bit is monitored to confirm whether the card is in busy
state by deselecting the card in busy state, and then
selecting the card, again.
0: Indicates that the card is in busy state.
1: Idle state waiting for command.
1
—
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
0
REQ
0
R
Interrupt Request
Indicates whether an interrupt is requested. An interrupt
request is the logical sum of the INTSTR0, INTSTR1, and
INTSTR2 flags. The INTSTR0, INTSTR1, and INTSTR2
flags are set by the enable bits in INTCR0, INTCR1, and
INTCR2.
0: No interrupts requested
1: An interrupt is requested



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