SH7721 datasheet(1105/1524 Pages) RENESAS

1105 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1043 of 1458

REJ09B0033-0300

31.3.10

Command Timeout Control Register (CTOCR)

CTOCR specifies a cycle to generate a timeout for the command response.

When receiving the command response, CTOUTC continues counting the transfer clock, and

enters the command timeout error state when the number of transfer clock reaches the number

specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is

set. To perform command timeout error handling, the command sequence should be aborted by

setting the CMDOFF bit to 1, and then the CTERI flag should be cleared.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 1



All 0



Reserved

These bits are always read as 0. The write value should

always be 0.

CTSEL0

R/W

0: 128 transfer clocks from command transmission completion

to response reception completion

1: 256 transfer clocks from command transmission completion

to response reception completion

Note:

When R2 response (17-byte command response) is required, a timeout is generated during

response reception if the CTSEL0 bit is set to 0. Therefore, set the CTSEL0 bit to 1.

SH7721 Datasheet(PDF) 1105 Page - Renesas Technology Corp