SH7721 datasheet(1106/1524 Pages) RENESAS

1106 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1044 of 1458

REJ09B0033-0300

31.3.11

Data Timeout Register (DTOUTR)

DTOUTR specifies a cycle to generate a data timeout. The 16-bit counter (DTOUTC) and a

prescaler count the peripheral clock to monitor the data timeout. The prescaler always counts the

peripheral clock, and outputs a count pulse for every 10000 peripheral clocks. The initial value of

DTOUTC is 0, and DTOUTC starts counting the prescaler output from the start of the command

sequence. DTOUTC is cleared when the command sequence has ended, or when the command

sequence has been aborted by setting the CMDOFF bit to 1, after which DTOUTC stops counting

the prescaler output.

When the command sequence does not end, DTOUTC continues counting the prescaler output,

and enters the data timeout error states when the number of prescaler output reaches the number

specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1

is set. To perform data timeout error handling, the command sequence should be aborted by

setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent extra-interrupt

generation.

For a command with data busy state, as the command sequence is terminated before entering the

data busy state, data timeout cannot be monitored. Timeout in the data busy state should be

monitored by firmware. When DTOUTR is set to 0, a data timeout is generated immediately after

the command sequence has started.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 0 DTOUTR All 1

R/W

Data timeout time/10000

Data timeout time is determined by peripheral clock cycle

DTOUTR setting value

× 10000.

SH7721 Datasheet(PDF) 1106 Page - Renesas Technology Corp