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7721 Datasheet(PDF) 179 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 179 Page - Renesas Technology Corp |
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179 / 577 page  7721 Group User’s Manual TIMER B 9–12 9.3 Timer mode 9.3.3 Operation in timer mode When the count start bit is set to “1,” the counter starts counting of the count source. When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. The timer Bi interrupt request bit is set to “1” at the underflow in . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 9.3.3 shows an example of operation in the timer mode. Stops counting. Restarts counting. FFFF16 n 000016 Time Count start bit Timer Bi interrupt request bit n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Set to “1” by software. 1 / fi ! (n+1) fi = frequency of count source (f2, f16, f64, f512) Cleared to “0” by software. Fig. 9.3.3 Example of operation in timer mode |
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