7721 datasheet(183/577 Pages) RENESAS

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7721 Group User’s Manual

TIMER B

9–16

9.4 Event counter mode

9.4.1 Setting for event counter mode

Figure 9.4.2 shows an initial setting example for registers relevant to the event counter mode.

Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.

INTERRUPTS.”

Note: The counter divides the count source by (n + 1).

Setting division ratio

Can be set to “000016” to “FFFF16” (n).

(b15)

(b8)

Timer B0 register (Addresses 5116, 5016)

Timer B1 register (Addresses 5316, 5216)

Count starts

0 0 : Counts at falling edge of external signal.

0 1 : Counts at rising edge of external signal.

1 0 : Counts at both of falling and rising edges of external signal.

1 1 : Do not select.

Selecting event counter mode and count polarity

Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16)

Setting count start bit to “1”

Count start register (Address 4016)

Timer B0 count start bit

Timer B1 count start bit

b3 b2

Setting interrupt priority level

Timer Bj interrupt control register (j = 0, 1)

(Addresses 7A16, 7B16)

Interrupt priority level select bits

When using interrupts, set these bits to one of levels 1 to 7.

When disabling interrupts, set these bits to level 0.

Setting port P5 direction register

Port P5 direction register (Address D16)

Clear the corresponding bit to “0.”

TB0IN pin

TB1IN pin

!: It may be “0” or “1.”

Selection of event counter mode

Count polarity select bits

Fig. 9.4.2 Initial setting example for registers relevant to event counter mode

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