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7721 Datasheet(PDF) 184 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 184 Page - Renesas Technology Corp |
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184 / 577 page  TIMER B 7721 Group User’s Manual 9–17 9.4 Event counter mode 9.4.2 Operation in event counter mode When the count start bit is set to “1,” the counter starts counting of the count source’s valid edges. When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. The timer Bj interrupt request bit is set to “1” at the underflow in . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 9.4.3 shows an example of operation in the event counter mode. Stops counting. Restarts counting . FFFF16 n 000016 Time Count start bit Timer Bj interrupt request bit n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Cleared to “0” by software. Set to “1” by software. Fig. 9.4.3 Example of operation in event counter mode |
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