7721 datasheet(190/577 Pages) RENESAS

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TIMER B

7721 Group User’s Manual

9–23

9.5 Pulse period/Pulse width measurement mode

9.5.3 Operation in pulse period/pulse width measurement mode

When the count start bit is set to “1,” the counter starts counting of the count source.

The counter value is transferred to the reload register when an valid edge of the measurement pulse

is detected. (Refer to section “(1) Pulse period/Pulse width measurement.”)

The counter value is cleared to “000016” after the transfer in , and the counter continues counting.

The timer Bj interrupt request bit is set to “1” when the counter value is cleared to “000016” in (Note).

The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request

bit is cleared to “0” by software.

The timer repeats operations to above.

Note: No timer Bj interrupt request occurs when the first valid edge is input after the counter starts counting.

(1)

Pulse period/Pulse width measurement

The measurement mode select bits (bits 2 and 3 at addresses 5B16 and 5C16) specify whether the

pulse period of an external signal is measured or its pulse width is done. Table 9.5.3 lists the

relationship between the measurement mode select bits and the pulse period/pulse width measurements.

Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice

versa are two cycles of the count source or more. Additionally, use software to identify whether the

measurement result indicates the “H” level or the “L” level width.

Table 9.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements

Pulse period/Pulse width measurement

Pulse period measurement

Pulse width measurement

Measurement interval (Valid edges)

From falling edge to falling edge (Falling edges)

From rising edge to rising edge (Rising edges)

From falling edge to rising edge, and vice versa

(Falling and rising edges)

(2)

Timer Bj overflow flag

A timer Bj interrupt request occurs when a measurement pulse’s valid edge is input or a counter

overflow occurs. The timer Bj overflow flag is used to identify the cause of the interrupt request, that

is, whether it is an overflow occurrence or a valid edge input.

The timer Bj overflow flag is set to “1” by an overflow. Accordingly, the cause of the interrupt request

occurrence is identified by checking the timer Bj overflow flag in the interrupt routine. When a value

is written to the timer Bj mode register with the count start bit = “1,” the timer Bj overflow flag is

cleared to “0” at the next count timing of the count source

The timer Bj overflow flag is a read-only bit.

Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow

flag for this detection.

Figure 9.5.3 shows the operation during pulse period measurement. Figure 9.5.4 shows the operation

during pulse width measurement.

7721 Datasheet(PDF) 190 Page - Renesas Technology Corp

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