7721 datasheet(247/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–44

11.4 Clock asynchronous serial I/O (UART) mode

11.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the receive enable state. After this, reception

starts when ST is detected and a transfer clock is generated.

____

In the case of selecting the RTS function, when the reception is enabled, the RTSi pin’s output level

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becomes “L” to inform the transmitter side that reception is enabled. When reception is started, the RTSi

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pin’s output level becomes “H.” Accordingly, by connecting the RTSi pin to the CTSi pin of the transmitter

side, the timing of transmission and that of reception can be matched. Figure 11.4.11 shows an connection

example.

The receive operation is described below.

The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register

synchronously with the transfer clock’s rising edge.

The contents of the UARTi receive register are shifted by 1 bit to the right.

Steps and are repeated at each rising edge of the transfer clock.

When one set of data has been prepared, in other words, when the shift has been performed several

times according to the selected data format, the UARTi receive register’s contents are transferred to the

UARTi receive buffer register.

Simultaneously with step , the receive complete flag is set to “1.” Additionally, a UARTi receive

interrupt request occurs and its interrupt request bit is set to “1.”

The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register

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is read out. The RTSi pin’s output level becomes “L” simultaneously with step (when selecting the RTS

function). Figure 11.4.12 shows an example of receive timing when the transfer data length = 8 bits.

TxDi

RxDi

TxDi

RxDi

Transmitter side

Receiver side

CTSi

RTSi

Fig. 11.4.11 Connection example

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