7721 datasheet(243/577 Pages) RENESAS

243 / 577 page

SERIAL I/O

7721 Group User’s Manual

11–40

11.4 Clock asynchronous serial I/O (UART) mode

The above timing diagram applies when

the following conditions are satisfied:

q Parity disabled

q 2 stop bits

q CTS function disabled

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1

SP SP

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level is “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from the external.)

Tc = 16(n + 1)/fi or 16(n + 1)/fEXT

fi: BRGi count source frequency (f2, f16, f64, f512)

fEXT: BRGi count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit enable bit

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Start bit

Cleared to “0” when interrupt request is accepted or cleared by software.

UARTi transmit register

UARTi transmit buffer register

Stopped because transmit enable bit = “0”

Stop bit Stop bit

Fig. 11.4.8 Example of transmit timing when transfer data length = 9 bits (when parity disabled,

____

selecting 2 stop bits, not selecting CTS function)

7721 Datasheet(PDF) 243 Page - Renesas Technology Corp