7721 datasheet(241/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–38

11.4 Clock asynchronous serial I/O (UART) mode

11.4.4 Transmit operation

When the receive conditions described in section “11.4.3 Method of transmission” are satisfied, a transfer

clock is generated and the following operations are automatically performed after 1 cycle of the transfer

clock has passed.

•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.

•The transmit buffer empty flag is set to “1.”

•The transmit register empty flag is cleared to “0.”

•A UARTi transmit interrupt request occurs and the interrupt request bit is set to “1.”

The transmit operations are described below:

Data in the UARTi transmit register is transmitted from the TxDi pin.

This data is transmitted bit by bit sequentially in order of ST

→DATA (LSB)→•••→DATA (MSB)→PAR

→SP according to the transfer data format.

The transmit register empty flag is set to “1” at the center of the stop bit (or the second stop bit when

selecting 2-stop bits), indicating completion of transmission. Additionally, whether the transmit conditions

for the next data are satisfied or not is examined.

When the transmit conditions for the next data are satisfied in step , the start bit is generated following

the stop bit, and the next data is transmitted. When performing transmission continuously, set the next

transmit data in the UARTi transmit buffer register during transmission (when the transmit register empty

flag = “0”). When the transmit conditions for the next data are not satisfied, the TxDi pin outputs “H” level

and the transfer clock stops.

Figures 11.4.6 and 11.4.7 show examples of transmit timing when the transfer data length = 8 bits, and

Figure 11.4.8 shows an example of transmit timing when the transfer data length = 9 bits.

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