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7906 Datasheet(PDF) 57 Page - Renesas Technology Corp |
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7906 Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 531 page  RESET 7906 Group User’s Manual Rev.2.0 3-14 3.3 State of internal area E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 EB16 EC16 ED16 EE16 EF16 EA16 b7 b0 b7 b0 INT5 interrupt control register INT6 interrupt control register INT7 interrupt control register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RW 00 00 00 0 RW 0 0 00 0 RW 0 00 0 RW 0 00 0 RW 0 00 0 RW 0 RW 00 00 0 RW 00 00 0 0 0 0 Address Register name Access characteristics State immediately after reset Timer A5 interrupt control register Timer A6 interrupt control register Timer A7 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register Notes 21 : Do not write to this register. (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) (Note 21) q Internal RAM area At hardware reset ................................................................................. Retains the state immediately before reset (Note 22). At software reset.................................................................................................... Retains the state immediately before reset. At termination of the stop or wait mode (when hardware reset is used for the termination.)....................................Retains the state immediately before the STP or WIT instruction is executed. At power-on reset..................................................................................................................................................... Undefined. Notes 22 : When a reset operation starts while writing to the internal RAM area is in process, the microcomputer will be reset before the completion of writing. Accordingly, the contents of the area where the writing was in process will become undefined. Fig. 3.3.9 State of SFR and internal RAM areas immediately after reset (8) |
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