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7906 Datasheet(PDF) 67 Page - Renesas Technology Corp |
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7906 Datasheet(HTML) 67 Page - Renesas Technology Corp |
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67 / 531 page  CLOCK GENERATING CIRCUIT 7906 Group User’s Manual Rev.2.0 4-8 4.2 Clocks Fig. 4.2.3 Setting procedure for clock control register 0 when using PLL frequency multiplier 2 ms elapsed ? b0 Clock control register 0 (Address BC16) b7 11 1 System clock select bit 0 : fPLL Setting of system clock select bit to “1.” N Y (Note 2) Notes 1: After reset, these bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 2: This decision is unnecessary If double is selected and the period of RESET = “L” is “the oscillation stabilizing time of an oscillator + 2 ms” or more. b0 Clock control register 0 (Address BC16) b7 PLL multiplication ratio select bits (Note 1) 0 1 : Double 1 0 : Triple 1 1 : Quadruple 00 1 b3 b2 System clock select bit 0 : fXIN PLL frequency multiplier is active, and pin VCONT is valid. 1 1 |
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