7906 datasheet(31/531 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7906 Group User’s Manual Rev.2.0

2-10

2.2 Bus interface unit (BIU)

Fig. 2.2.1 Bus and BIU

2.2 Bus interface unit (BIU)

The bus interface unit (hereafter called “BIU”) performs the following two operations:

q Instruction prefetch

q Data transfer (read and write)

Figure 2.2.1 shows the bus and BIU.

BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU

registers.

M37906

Internal code bus (CB0 to CB31)

(CPU)

SFR : Special Function Register

❈ The CPU bus and internal bus are independent of one another.

Internal control signal

Internal buses

Internal data bus (DB0 to DB15)

Internal address bus (AD0 to AD23)

(BIU)

CPU bus

Central

processing

unit

Bus

interface

unit

Internal

memory

Internal

peripheral

devices

(SFR)

Program address register

Instruction queue buffer

Data address register

Data buffer

b23

b31

Name

Program

address

Instruction

queue buffer

Data address

Data buffer

Functions

Indicates a storage address of the

instruction to be fetched into an

instruction queue buffer, next.

Temporarily stores an instruction

which has been fetched.

Indicates an address from which data

will be read or to which data will be

written, next.

Temporarily stores data which has

been read from memory•I/O device

by BIU or which will be written to

memory•I/O device by the CPU.

Fig. 2.2.2 BIU registers’ structure

Table 2.2.1 Functions of BIU registers

In the M37906, the internal buses are used when the CPU accesses the internal area (the internal memory

and SFR).

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