7906 datasheet(93/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-14

6.7 Sequence from acceptance of interrupt request until execution of interrupt routine

Fig. 6.7.2 INTACK sequence timing (at minimum)

6.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the

interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple

interrupts. (Refer to section “6.9 Multiple interrupts.”)

At acceptance of a watchdog timer interrupt request, a zero division request, or address matching detection

interrupt request or at reset, a value in Table 6.7.1 is set into the IPL.

Table 6.7.1 Change in IPL at acceptance of interrupt request

Interrupts

Reset

Watchdog timer

Zero division

Address matching detection

Other interrupts

Change in IPL

Level 0 (“0002”) is set.

Level 7 (“1112”) is set.

Not changed.

Accepted interrupt’s priority level is set.

q When stack pointer (S)’s contents are even at acceptance of an interrupt request with bus cycle = 2

Undefined

AD23–AD16

BLW

BHW

fsys

INTACK sequence

φCPU

[S]: Contents of stack pointer (S)

FFXX16: Vector address

fsys,

φCPU: Internal clock (See Figure 4.2.1.)

AD23–AD0: Internal address bus

DB15–DB0: Internal data bus

AD15–AD0

DB15–DB8

DB7–DB0

Undefined

0000

[S] – 2

[S] – 4

FFXX16

AD15–AD0

[S]

Undefined

IPL

PCH

PSH

AD15–AD8

Next instruction

—

Undefined

(low-order)

PCL

PSL

AD7–AD0

Next instruction

Note: These are internal signals and are not output to the external.

Vector address

(Note)

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