7906 datasheet(94/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-15

6.7.2 Push operation for registers

The push operation for registers performed in the INTACK sequence depends on whether the contents of

the stack pointer (S) at acceptance of an interrupt request are even or odd.

When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the

processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the

stack pointer (S) are odd, each of PC and PS is pushed in a unit of 8 bits. Figure 6.7.3 shows the push

operation for registers.

In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and

processor status register (PS) are pushed onto the stack area. Other necessary registers must be pushed

by software at the start of the interrupt routine.

By using the PSH instruction, all CPU registers, except the stack pointer (S), can be pushed with 1

instruction.

6.7 Sequence from acceptance of interrupt request until execution of interrupt routine

Fig. 6.7.3 Push operation for registers

Pushed in 3 times.

➂ Pushed in a unit of 16 bits.

➀

➁ Pushed in a unit of 16 bits.

(1) When contents of stack pointer (S) are even

Program bank register (PG)

Address

[S] – 4 (even)

[S] – 3 (odd)

[S] – 2 (even)

[S] – 1 (odd)

[S] (even)

Order for push

[S] – 5 (odd)

Address

[S] – 4 (odd)

[S] – 3 (even)

[S] – 2 (odd)

[S] – 1 (even)

[S] (odd)

➂

➀

➁

➄

➃

Pushed in a unit of 8 bits.

Order for push

Pushed in 5 times.

[S] – 5 (even)

Low-order byte of program counter (PCL)

High-order byte of program counter (PCH)

(2) When contents of stack pointer (S) are odd

Low-order byte of processor status register (PSL)

Program bank register (PG)

High-order byte of processor status register (PSH)

Low-order byte of program counter (PCL)

High-order byte of program counter (PCH)

✽ [S] is the initial address that the stack pointer (S) indicates at acceptance of an interrupt request.

The S’s contents become “[S] – 5” after all of the above registers are pushed.

Low-order byte of processor status register (PSL)

High-order byte of processor status register (PSH)

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