7906 datasheet(92/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-13

6.7 Sequence from acceptance of interrupt request until execution of

interrupt routine

The sequence from acceptance of an interrupt request until execution of the interrupt routine is described

below.

When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.”

And then, the interrupt processing starts from the cycle just after completion of the instruction execution

which was executed at acceptance of the interrupt request. Figure 6.7.1 shows the sequence from occurrence

of an interrupt request until execution of the interrupt routine. After execution of an instruction at acceptance

of the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a

branch is made to the start address of the interrupt routine allocated in addresses 016 to FFFF16.

In the INTACK sequence, the following are automatically performed in ascending sequence from ➀ to ➅.

➀ The contents of the program bank register (PG) just before performing the INTACK sequence are pushed

onto stack.

➁ The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto

stack.

➂ The contents of the processor status register (PS) just before performing the INTACK sequence is

pushed onto stack.

➃ The interrupt disable flag (I) is set to “1.”

➄ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).

➅ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt

vector address are set into the program counter (PC).

Performing the INTACK sequence requires at least 15 cycles of fsys. Figure 6.7.2 shows the INTACK sequence

timing. After the INTACK sequence is completed, the instruction execution starts from the start address of

the interrupt routine.

6.7 Sequence from acceptance of interrupt request until execution of interrupt routine

@ : Interrupt priority level detection time

Interrupt request occurs.

Interrupt request is accepted.

Instruction

INTACK sequence

Instructions in interrupt routine

Interrupt response time

Time

➀ Time from occurrence of an interrupt request until comparison of an instruction execution which

is in progress at that time.

➁ Time from execution start of an instruction next to ➀ until completion of execution of the instruction

which was in progress at detection completed.

➂ Time required to perform the INTACK sequence (15 cycles of

φ at minimum)

➀

➁

➂

Fig. 6.7.1 Sequence from occurrence of interrupt request until execution of interrupt routine

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