OPA2673 datasheet(27/40 Pages) TI

27 / 40 page

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NoiseGain

Driving Capacitive Loads

Output Current and Voltage

OPA2673

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values used in the Typical Characteristics are also

the zero-current output voltage limit, respectively. The

correcting for board parasitic not considered in the

four quadrants give a more detailed view of the

simplified analysis leading to Equation 15. The values

OPA2673 output drive capabilities, noting that the

shown in Figure 83 give a good starting point for

graph is bounded by a safe operating area of 2W

designs where bandwidth optimization is desired.

maximum internal power dissipation (in this case, for

one channel only). Superimposing resistor load lines

onto the plot shows that the OPA2673 can drive ±4V

into 10

Ω or ±45V into 25Ω without exceeding the

output capabilities or the 2W dissipation limit. A 100

Ω

load line (the standard test circuit load) shows the full

±4.8V output swing capability, as stated in the

Electrical

Characteristics

table.

The

minimum

specified output voltage and current over temperature

are set by worst-case simulations at the cold

temperature extreme. Only at cold startup do the

output current and voltage decrease to the numbers

shown in the Electrical Characteristics table. As the

output

transistors

deliver

power,

the

junction

temperatures

increase,

decreasing

the

VBEs

(increasing the available output voltage swing), and

increasing the current gains (increasing the available

output

current).

steady-state

operation,

the

Figure 83. Feedback Resistor vs Noise Gain

available output voltage and current is always greater

than

that

shown

the

over-temperature

The total impedance going into the inverting input

specifications because the output stage junction

may be used to adjust the closed-loop signal

temperatures is higher than the minimum specified

bandwidth. Inserting a series resistor between the

operating ambient.

inverting input and the summing junction increases

the

feedback

impedance

(the

denominator

Equation 14), decreasing the bandwidth. The internal

One of the most demanding and yet very common

buffer output impedance for the OPA2673 is slightly

load conditions for an op amp is capacitive loading.

influenced by the source impedance coming from of

Often, the capacitive load is the input of an

the noninverting input terminal. High-source resistors

analog-to-digital

converter

(ADC)—including

also have the effect of increasing RI, decreasing the

additional

external

capacitance

that

may

bandwidth. For those single-supply applications that

recommended to improve the ADC linearity. A

develop a midpoint bias at the noninverting input

high-speed, high open-loop gain amplifier such as the

through

high

valued

resistors,

the

decoupling

OPA2673 can be very susceptible to decreased

capacitor

essential

for

power-supply

ripple

stability and closed-loop response peaking when a

rejection, noninverting input noise current shunting,

capacitive load is placed directly on the output pin.

and to minimize the high-frequency value for RI in

When the amplifier open-loop output resistance is

Figure 82.

considered,

this

capacitive

load

introduces

additional pole in the signal path that can decrease

the phase margin. Several external solutions to this

The OPA2673 provides output voltage and current

problem have been suggested.

capabilities that are unsurpassed in a low-cost dual

When the primary considerations are frequency

monolithic op amp. Under no-load conditions at

response flatness, pulse response fidelity, and/or

+25°C, the output voltage typically swings closer than

distortion, the simplest and most effective solution is

1.1V to either supply rail; the tested (+25°C) swing

to isolate the capacitive load from the feedback loop

limit is within 1.2V of either rail. Into a 4

Ω load (the

by inserting a series isolation resistor between the

minimum tested load), it delivers more than ±460mA.

amplifier

output

and

the

capacitive

load.

This

The

specifications

described

previously,

though

approach does not eliminate the pole from the loop

familiar in the industry, consider voltage and current

response, but rather shifts it and adds a zero at a

limits separately. In many applications, it is the

higher frequency. The additional zero acts to cancel

voltage times current (or V-I product) that is more

the phase lag from the capacitive load pole, thus

relevant to circuit operation. Refer to the Output

increasing the phase margin and improving stability.

Voltage and Current Limitations plot in the Typical

The Typical Characteristics show the Differential RS

Characteristics (Figure 6). The X- and Y-axes of this

vs Capacitive Load (Figure 27) and the resulting

graph show the zero-voltage output current limit and

frequency response at the load. Parasitic capacitive

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