ATSAM3703 datasheet(11/36 Pages) ATMEL

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6237A–DRMSD–29-May-06

ATSAM3703

X1 - X2

64, 63

External crystal connection. Standard frequencies are 6.9552

MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is

12.5 MHz. An external clock (max. 1.8Vpp) can be connected

to X1 using AC coupling (22pF). A built-in PLL multiplies the

clock frequency by 4 for internal use.

RESET

Master reset Schmitt trigger input, active low. RESET should

be held low during at least 10ms after power is applied. On the

rising edge of RESET, the chip enters an initialization routine,

which may involve firmware download from an external

SmartMedia, or host.

STIN

Serial test input. This is a 57.6 kbauds asynchronous input

used for firmware debugging. This pin is tested at power-up.

The built-in debugger starts if STIN is found high. STIN has a

built-in pull-down. It should be grounded or left open for normal

operation.

STOUT

Out

Serial test output. 57.6 kbauds async output used for firmware

debugging.

PDWN

Power down input, active low. High level on this pin is typ.

VC18. When PDWN is low, the oscillator and PLL are stopped,

the power switch opens, and the chip enters a deep sleep

mode (1µA typ. consumption when power switch is used). To

exit from power down, PDWN has to be set high then RESET

applied. Alternate programmable power-downs are available

which allow warm restart of the chip.

TEST

Test input. Should be grounded or left open.

Table 6-1.

ATSAM3703 Pin Description (Continued)

Pin Name

Pin Number

Type

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