ATSAM3703 datasheet(31/36 Pages) ATMEL

31 / 36 page

6237A–DRMSD–29-May-06

ATSAM3703

11. Recommended Board Layout

Like all HCMOS high integration ICs, the following rules for board layout are mandatory for reli-

able operations.

11.1

GND, VC33, VC25, VC18 Distribution, Decoupling

All GND, VC33, VC25, VC18 pins should be connected. A GND plane is strongly recommended.

The board GND, VC33, VC25 and VC18 distribution should be in grid form.

Recommended VC18 decoupling is 0.1µF at each VC18 pin of the IC with an additional 10µFT

decoupling close to the crystal. Minimum recommended VC25 decoupling is 0.1µF at pin 22, 42

and 55. VC33 requires a single 0.1µF decoupling.

11.2

Crystal

The paths between the crystal, the crystal compensation capacitors and the IC should be short

and shielded. The ground return from the compensation capacitors filter should be the GND

plane from the IC.

11.3

Buses

Parallel layout from D0-D7 and WA0-WA11/WDQ0-WDQ3 should be avoided. The D0-D7 bus is

an asynchronous type bus. Even on short distances, it can induce pulses on WA0-

WA11/WDQ0-WDQ3 which can corrupt address and/or data on these buses.

A ground plane should be implemented below the D0-D7 bus, which connects both to the host

and to the IC GND.

A ground plane should be implemented below the WA0-WA11/WDQ0-WDQ3 bus, which con-

nects both to the SDRAM or DDR SDRAM grounds and to the IC.

11.4

DDR SDRAM and SDRAM

The routing of all signals must be as symmetric as possible. This applies particularly to WDQS,

WDQ3, WDQ2, WDQ1 and WDQ0 signals.

The routing of all signals should be kept as short as possible.

VREF must be equal to VC25/2, generated with a resistive divider. Both resistors must have the

same value (1% precision). Suggested range is 50 - 150 Ohm. Proper decoupling at each VREF

pin (controller, VREF source and RAM device) is recommended.

The SSTL2 signals (DDR) must use a parallel termination (47 Ohm, for example). This termina-

tion must be connected to VTT (VC25/2). This VTT is generated from a special component (able

to source or to sink current) using VREF as reference. This termination must be placed just after

DDR device.

11.5

Analog Section

A specific AGND ground plane should be provided, which connects by a single trace to the GND

ground. No digital signals should cross the AGND plane. Refer to the Codec vendor recom-

mended layout for correct implementation of the analog section.

ATSAM3703 Datasheet(PDF) 31 Page - ATMEL Corporation

ATSAM3703 Datasheet(HTML) 31 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL