ATSAM3703 datasheet(30/36 Pages) ATMEL

30 / 36 page

6237A–DRMSD–29-May-06

ATSAM3703

10. Reset and Power Down

During power-up, the RESET input should be held low until the crystal oscillator and PLL are

stabilized, which takes max. 10ms.

After the low to high transition of RESET, the following occurs:

• All P24s enter an idle state.

• P16 program execution starts in built-in ROM.

The power-up sequence is as follows:

• STIN is sensed. If HIGH, then the built-in debugger is started.

• Addresses 0 &1 from internal EEPROM are checked. If “DR” is read, then control is

transferred to address 400H from internal EEPROM.

•SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect

(SMPD). When detected, the firmware is downloaded from SmartMedia reserved sector 1

and started.

• Firmware download from an host processor is assumed. (Download in 8K x 24 internal RAM)

The byte 0ACh is written to the host, this rises IRQ. The host can recognize that the

chip is ready to accept program download. Higher speed transfer can be reach by poll-

ing the parallel interface status (CS=0, A0=1, RD=0).

The host sends the firmware size (in words) on two bytes (low byte first).

The host sends the ATSAM3703 firmware. The firmware should begin with string “DR”.

The byte 0ACh is written to the host, this rises IRQ. The host can recognize that the

chip has accepted the firmware.

ATSAM3703 starts the firmware.

If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is

used, then the chip enters a deep power down sleep mode, as power is removed from the core.

To exit power down, PDWN has to be asserted high, then RESET applied.

Other power reduction features allowing warm restart are controlled by firmware:

• P24s can be individually stopped.

• The clock frequency can be internally divided by 256.

ATSAM3703 Datasheet(PDF) 30 Page - ATMEL Corporation