ATSAM3703 datasheet(26/36 Pages) ATMEL

26 / 36 page

6237A–DRMSD–29-May-06

ATSAM3703

ATSAM3703 to SDRAM

The outputs of ATSAM3703 meet constraints as in Table 9-12.

SDR to ATSAM3703

The data from SDR to ATSAM3703 must meet following timing requirements. These parameters

are applicable at input of ATSAM3703, and must include effects of SDR device and effects of

board layout.

9.4.4

Address Mapping

For information, the mapping in Table 9-14 is applied from the internal async bus address

AAD[22:0] to the SDRAM address.

Note:

WA[1:0] = 00 at CAS time means that for each read or write operation at a specified address, four

nibbles are read or write in the burst sequential order (0,1, 2, 3). Other sequential orders are not

allowed.

Table 9-12.

ATSAM9703 Output Constraints

Symbol

Parameter

Value(50 MHz)

Value(100 MHz)

tIH

Address and control hold time

min 8.8 ns

min 3.8 ns

tIS

Address and control setup time

min 8.3 ns

min 3.3 ns

DQ and DM setup time

min 14.3 ns

min 6.8 ns

tDH

DQ and DM hold time

min 3.8 ns

min 1.4 ns

Table 9-13.

Timing Requirements

Parameter

Value

DQ setup time

min 2.0 ns

DQ hold time

min 1.8 ns

Table 9-14.

Address Mapping

ATSAM3703 Address Bus

Value at RAS time

Value at CAS time

WBA0

AAD0

WBA1

AAD1

WA0

AAD10

0 (see note)

WA1

AAD11

0 (see note)

WA2

AAD12

AAD2

WA3

AAD13

AAD3

WA4

AAD14

AAD4

WA5

AAD15

AAD5

WA6

AAD16

AAD6

WA7

AAD17

AAD7

WA8

AAD18

AAD8

WA9

AAD19

AAD9

WA10

AAD20

Auto-Precharge

WA11

AAD21

AAD22

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