PCM1795 datasheet(45/58 Pages) TI

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DMF[1:0]: Analog-FIR Performance Selection

OS[1:0]: Analog-FIR Operation-Speed Selection

TDMCA INTERFACE FORMAT

TDMCA Mode Determination

Pre-TDMCA Frame

BCK

LRCK

TDMCAFrame

Command

2BCKs

PCM1795

www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009

Default value: 00

DMF[1:0]

Analog-FIR Performance Selection

FIR-1 (default)

FIR-2

FIR-3

FIR-4

Plots for the four analog finite impulse response (FIR) filter responses are shown in the Analog FIR Filter

Performance in DSD Mode section of the Typical Characteristics.

Default value: 00

OS[1:0]

Operating Speed Selection

fDBCK (default)

fDBCK/2

Reserved

fDBCK/4

The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set

before setting the DSD bit to '1'.

The PCM1795 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the

host control serial interface. TDMCA format is designed not only for the multichannel buffered serial port

description (McBSP) of TI DSPs but also for any programmable devices. TDMCA format can transfer not only

audio data but also command data, so that it can be used together with any kind of device that supports TDMCA

format. The TDMCA frame consists of a command field, extended command field, and some audio data fields.

Those audio data are transported to IN devices (such as a DAC) and/or from OUT devices (such as an ADC).

The PCM1795 is an IN device. LRCK and BCK are used with both IN and OUT devices so that the sample

frequency of all devices in a system must be the same. The TDMCA mode supports a maximum of 30 device

IDs. The maximum number of audio channels depends on the BCK frequency.

The PCM1795 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse

duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%.

Figure 61 shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1795 enters TDMCA

mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA

frame after entering TDMCA mode.

Figure 61. LRCK and BCK Timing for Determination of TDMCA Mode

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