PCM1795 datasheet(25/58 Pages) TI

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Write Register

Data Type

WriteData2

Transmitter

ACK

NACK

SlaveAddress

RegisterAddress

WriteData1

M:MasterDevice

S:SlaveDevice

St:StartCondition

Sp:StopCondition

ACK:Acknowledge

NACK:NotAcknowledged

:Write

Read Register

Data Type

Data

Transmitter

ACK

NACK

SlaveAddress

RegisterAddress

SlaveAddress

M:MasterDevice

S:SlaveDevice

St:StartCondition

Sr:RepeatedStartCondition

Sp:StopCondition

R:Read

:Write

ACK:Acknowledge

NACK:NotAcknowledged

Noise Suppression

SCL

SDA

Noise

PCM1795

www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009

A master can write to any PCM1795 registers using single or multiple accesses. The master sends a PCM1795

slave address with a write bit, a register address, and the data. If multiple access is required, the address is that

of the starting register, followed by the data to be transferred. When the data are received properly, the index

undefined registers are accessed, the PCM1795 does not send an acknowledgment. Figure 46 shows a diagram

of the write operation.

Figure 46. Write Operation

A master can read the PCM1795 register. The value of the register address is stored in an indirect index register

in advance. The master sends a PCM1795 slave address with a read bit after storing the register address. Then

the PCM1795 transfers the data that the index register points to. When the data are transferred during a multiple

access, the index register is incremented by '1' automatically. (When first going into read mode immediately

following a write, the index register is not incremented. The master can read the register that was previously

written.) When the index register reaches 0x7F, the next value is 0x00. The PCM1795 outputs some data when

the index register is 0x10 to 0x1F, even if it is not defined in Table 9. Figure 47 shows a diagram of the read

operation.

Figure 47. Read Operation

The PCM1795 incorporates noise suppression using the system clock (SCK). However, there must be no more

than two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz

in fast mode. However, it works incorrectly under the following conditions:

Case 1:

1. t(SCK) > 120 ns (t(SCK): period of SCK)

2. t(HI) + t(D–HD) < t(SCK) × 5

3. Spike noise exists on the first half of the SCL high pulse.

4. Spike noise exists on the SDA high pulse just before SDA goes low.

Figure 48. Case 1

When these conditions occur at the same time, the data are recognized as low.

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