DM9013 datasheet(36/75 Pages) DAVICOM

36 / 75 page

DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

CFH:

Bit

Name

Default

Description

7:6

TOS3F

PE3,RW

If bit 53H.7 =1 :TOS[7:2]=3FH

5:4

TOS3E

PE3,RW

If bit 53H.7 =1 :TOS[7:2]=3EH

3:2

TOS3D

PE3,RW

If bit 53H.7 =1 :TOS[7:2]=3DH

1:0

TOS3C

PE3,RW

If bit 53H.7 =1 :TOS[7:2]=3CH

6.58 VLAN Priority Map Registers (D0H~D1H)

D0H:

Bit

Name

Default

Description

7:6

TAG3

PE1,RW

VLAN priority tag value = 03H

5:4

TAG2

PE1,RW

VLAN priority tag value = 02H

3:2

TAG1

PE0,RW

VLAN priority tag value = 01H

1:0

TAG0

PE0,RW

VLAN priority tag value = 00H

D1H:

Bit

Name

Default

Description

7:6

TAG7

PE3,RW

VLAN priority tag value = 07H

5:4

TAG6

PE3,RW

VLAN priority tag value = 06H

3:2

TAG5

PE2,RW

VLAN priority tag value = 05H

1:0

TAG4

PE2,RW

VLAN priority tag value = 04H

6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)

Bit

Name

Default

Description

7:0

MRCMDX

X,RO

Read data from RX SRAM. After the read of this command, the read pointer of

internal SRAM is unchanged. And the DM9013 starts to pre-fetch the SRAM data

to internal data buffers.

6.60 Memory Data Read Command with Address Increment Register (F2H)

When register FFH bit 7 is “0”, register F5H value will be returned to 0000H, if 16K-byte boundary is reached.

When register FFH bit 7 is “1”, register F5H value will be returned to 0000H, if processor port receive memory byte boundary

address RX memory size, defined in register 3FH with default 1F00H, is reached.

Bit

Name

Default

Description

7:0

MRCMD

X,RO

Read data from RX SRAM. After the read of this command, the read pointer is

increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit

respectively)

6.61 Memory Data Read address Register (F4H)

When register FFH bit 7 is “0”, register F5H and F4H can be used as memory byte address to read internal 64K-byte memory.

When register FFH bit 7 is “1”, register F5H and F4H can be used as processor port receive memory byte address with

memory space range from 0 to (RX memory size - 1), defined in register 3FH with default 1EFFH.

Bit

Name

Default

Description

7:0

MDRAL

PHS0,RW Memory Data Read_ address Low Byte

DM9013 Datasheet(PDF) 36 Page - Davicom Semiconductor, Inc.

DM9013 Datasheet(HTML) 36 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL