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DM9013 Datasheet(PDF) 37 Page - Davicom Semiconductor, Inc. |
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DM9013 Datasheet(HTML) 37 Page - Davicom Semiconductor, Inc. |
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37 / 75 page ![]() DM9013 3-port switch with Processor Interface Preliminary datasheet 37 DM9013-15-DS-P03 April 9, 2009 6.62 Memory Data Read address Register (F5H) Bit Name Default Description 7-6 RESERVED P0,RO Reserved 5:4 MDRAH65 PHS0,RW Port number 3:0 MDRAH40 PHS0,RW Memory Data Read_ address [11:8] 6.63 Memory Data Write Command without Address Increment Register (F6H) Bit Name Default Description 7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is unchanged 6.64 Memory Data Write Command with Address Increment Register (F8H) Bit Name Default Description 7:0 MWCMD X,WO Write Data to TX SRAM After the write of this command, the write pointer is increased by 1, 2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.65 Memory Data Write address Register (FAH) Bit Name Default Description 7:0 MDRAL PHS0,RW Memory Data Write_ address Low Byte 6.66 Memory Data Write address Register (FBH) Bit Name Default Description 7,6 RESERVED P0,RO Reserved 5:4 MDRAH65 PHS0,RW Port number 3:0 MDRAH40 PHS0,RW Memory Data Write_ address [11:8] 6.67 TX Packet Length Register (FCH~FDH) Bit Name Default Description 7:0 TXPLH PHS0,RW TX Packet Length High byte 7:0 TXPLL PHS0,RW TX Packet Length Low byte 6.68 Interrupt Status Register (FEH) Bit Name Default Description 7:6 IOMODE T0, RO Bit 7 Bit 6 0 0 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 Reserved 5 LNKCHG PHS0,RW/C1 Link Status Change of port 0 or 1 4 CNT_ERR PHS0,RW/C1 BLK Table Counter error 3 ROO PHS0,RW/C1 Receive Overflow Counter Overflow 2 ROS PHS0,RW/C1 Receive Overflow 1 PT PHS0,RW/C1 Packet Transmitted 0 PR PHS0,RW/C1 Packet Received |
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