DM9013 datasheet(26/75 Pages) DAVICOM

26 / 75 page

DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

6.29 Processor Data Bus driving capability Register (38H)

Bit

Name

Default

Description

RESERVED

0,RW

reserved

6:5

ISA_CURR

P01,RW

SD Bus Current Driving/Sinking Capability

00: 2mA

01: 4mA (default)

10: 6mA

11: 8mA

4:3

Reserved

P0,RW

Reserved

STEP

P0,RW

Data Bus Output stepping

1: disabled

0: enabled

IOW_SPIKE

P0,RW

Eliminate IOW spike

1: eliminate about 2ns IOW spike

IOR_SPIKE

P1,RW

Eliminate IOR spike

1: eliminate about 2ns IOR spike

6.30 Port 2 driving capability Register (3AH)

Bit

Name

Default

Description

Reserved

0,RO

Reserved

6:5

P2_CURR

P01,RW

Port 2 TXD/TXECurrent Driving/Sinking Capability

00: 2mA

01: 4mA (default)

10: 6mA

11: 8mA

4:0

RESERVED

P01,RW

reserved

6.31 IRQ Pin Control Register (39H)

Bit

Name

Default

Description

7:2

Reserved

PS0,RO

Reserved

IRQ_TYPE

PET0,RW

IRQ Pin Output Type Control

0: IRQ direct output

1: IRQ Open-Collector output

IRQ_POL

PET0,RW

IRQ Pin Polarity Control

0: IRQ active high

1: IRQ active low

6.32 TX Block Size Control Register (3FH)

Bit

Name

Default

Description

7:6

Reserved

PS0,RO

Reserved

5:0

TX_SIZE

P20h,RW

TX Block Size in 2-Port Mode

This value defines the transmit block size in 256-byte unit.

TX memory size = TX_SIZE * 256 bytes

And then

RX memory size = 16KB – (TX_SIZE + 1)*256-Byte

Note: The value of TX_SIZE should be between 14H and 30H

DM9013 Datasheet(PDF) 26 Page - Davicom Semiconductor, Inc.

DM9013 Datasheet(HTML) 26 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL