LPC1313 datasheet(24/60 Pages) NXP

24 / 60 page

LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

24 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.17.5 Power control

The LPC1311/13/42/43 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Selected peripherals have

their own clock divider which provides even better power control.

7.17.5.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.17.5.2

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks can be shut

down for increased power savings. The user can configure the Deep-sleep mode to a

large extent, selecting any of the oscillators, any of the PLLs, the USB PHY (LPC134x

only), BOD, the ADC, and the flash to be shut down or remain powered during Deep-sleep

mode. The user can also select which of the oscillators and analog blocks will be powered

up after the chip exits from Deep-sleep mode.

The GPIO pins (up to 40 pins total) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The timing of the wake-up process from Deep-sleep mode depends on which blocks are

selected to be powered down during deep-sleep.

For lowest power consumption, the clock source should be switched to IRC before

entering Deep-sleep mode, all oscillators and PLLs should be turned off during

deep-sleep, and the IRC should be selected as clock source when the chip wakes up from

deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock

signal after start-up.

If power consumption is not a concern, any of the oscillators and/or PLLs can be left

running in Deep-sleep mode to obtain short wake-up times when waking up from

deep-sleep.

7.17.5.3

Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the

WAKEUP pin.

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