LPC1313 datasheet(43/60 Pages) NXP

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LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

43 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.4 I/O pins

[1]

Applies to standard port pins and RESET pin.

10.5 I2C-bus

[1]

See the I2C-bus specification UM10204 for details.

[2]

Parameters are valid over operating temperature range unless otherwise specified.

[3]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5]

Cb = total capacitance of one bus line in pF.

[6]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[7]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

Table 15.

Dynamic characteristics: I/O pins[1]

Tamb = −40 °C to +85 °C; 2.0 V ≤ VDD ≤ 3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

rise time

pin configured as output

3.0

5.0

fall time

pin configured as output

2.5

5.0

Table 16.

Dynamic characteristic: I2C-bus pins[1]

Tamb = −40 °C to +85 °C.[2]

Symbol

Parameter

Conditions

Min

Max

Unit

fSCL

SCL clock

frequency

Standard-mode

100

kHz

Fast-mode

400

kHz

Fast-mode Plus

MHz

fall time

[4][5][6][7]

of both SDA and SCL

signals

Standard-mode

-300

Fast-mode

20 + 0.1

× C

300

Fast-mode Plus

120

tLOW

LOW period of the

SCL clock

Standard-mode

4.7

μs

Fast-mode

1.3

μs

Fast-mode Plus

0.5

μs

tHIGH

HIGH period of the

SCL clock

Standard-mode

4.0

μs

Fast-mode

0.6

μs

Fast-mode Plus

0.26

μs

tHD;DAT

data hold time

[3][4][8]

Standard-mode

μs

Fast-mode

μs

Fast-mode Plus

μs

tSU;DAT

data set-up time

[9][10]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

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