LPC1313 datasheet(14/60 Pages) NXP

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LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

14 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[1]

See Figure 31 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset

the chip and wake up from Deep power-down mode.

[2]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30).

[3]

I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[4]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 30).

[5]

Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[6]

When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to TCM interfaces: one bus dedicated for instruction

fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for

simultaneous operations if concurrent operations target different devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptible/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller, and multiple core buses

capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

PIO2_0/DTR

1[2]

I/O

PIO2_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

PIO3_2

28[2]

I/O

PIO3_2 — General purpose digital input/output pin.

PIO3_4

13[2]

I/O

PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).

PIO3_5

14[2]

I/O

PIO3_5 — General purpose digital input/output pin (LPC1311/13 only).

USB_DM

13[5]

I/O

USB_DM — USB bidirectional D

− line (LPC1342/43 only).

USB_DP

14[5]

I/O

USB_DP — USB bidirectional D+ line (LPC1342/43 only).

VDD

6; 29

3.3 V supply voltage to the internal regulator, the external rail, and the ADC.

Also used as the ADC reference voltage.

XTALIN

4[6]

Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT

5[6]

Output from the oscillator amplifier.

VSS

Thermal pad. Connect to ground.

Table 4.

LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol

Type

Description

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