LPC1313 datasheet(45/60 Pages) NXP

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LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

45 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.6 SSP interface

[1]

Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2]

Tamb = −40 °C to 85 °C.

[3]

Tcy(clk) = 12 × Tcy(PCLK).

[4]

Tamb = 25 °C; VDD = 3.3 V.

Table 17.

Dynamic characteristics: SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Max

Unit

Tcy(PCLK)

PCLK cycle time

13.9

Tcy(clk)

clock cycle time

[1]

27.8

SSP master

tDS

data set-up time

in SPI mode;

2.4 V

≤ V

DD ≤ 3.6 V

[2]

2.0 V

≤ V

DD < 2.4 V

[2]

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time

in SPI mode

[2]

-10

th(Q)

data output hold time

in SPI mode

[2]

SSP slave

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

× T

cy(PCLK) + 4

tv(Q)

data output valid time

in SPI mode

[3][4]

-3

× T

cy(PCLK) + 11

th(Q)

data output hold time

in SPI mode

[3][4]

-2

× T

cy(PCLK) + 5

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