LPC1313 datasheet(25/60 Pages) NXP

25 / 60 page

LPC1311_13_42_43_2

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Product data sheet

Rev. 02 — 6 May 2010

25 of 60

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.18 System control

7.18.1 Reset

Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset,

power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the flash controller.

When the internal reset is removed, the processor begins executing at address 0, which is

initially the reset vector mapped from the boot block. At that point, all of the processor and

peripheral registers have been initialized to predetermined values.

7.18.2 Brownout detection

The LPC1311/13/42/43 includes four levels for monitoring the voltage on the VDD pin. If

this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal

to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading

a dedicated status register. An additional threshold level can be selected to cause a

forced reset of the chip.

7.18.3 Code security (Code Read Protection - CRP)

This feature of the LPC1311/13/42/43 allows user to enable different levels of security in

the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. In-Application

Programming (IAP) commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP (NO_ISP

mode). For details see the LPC13xx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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