DAC8728 datasheet(7/52 Pages) TI

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DAC8728

www.ti.com

SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009

ELECTRICAL CHARACTERISTICS: Single-Supply

All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x =

DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.

DAC8728

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

Resolution

Bits

Linearity error

Measured by line passing through codes 0100h and FFFFh

±4

LSB

Differential linearity error

Measured by line passing through codes 0100h and FFFFh

±1

LSB

TA = +25°C, before user calibration, gain = 6, code = 0100h

±10

LSB

Unipolar zero error

TA = +25°C, before user calibration, gain = 4, code = 0100h

±15

LSB

TA = +25°C, after user calib., gain = 4 or 6, code = 0100h

±1

LSB

Unipolar zero error TC

Gain = 4 or 6, code = 0100h

±0.5

±3

ppm FSR/°C

TA = +25°C, gain = 6

±10

LSB

Gain error

TA = +25°C, gain = 4

±15

LSB

Gain error TC

Gain = 4 or 6

±1

±3

ppm FSR/°C

TA = +25°C, before user calibration, gain = 6, code = FFFFh

±10

LSB

Full-scale error

TA = +25°C, before user calibration, gain = 4, code = FFFFh

±15

LSB

TA = +25°C, after user calib., gain = 4 or 6, code = FFFFh

±1

LSB

Full-scale error TC

Gain = 4 or 6, code = FFFFh

±0.5

±3

ppm FSR/°C

Measured channel at code = 8000h, full-scale change on any

DC crosstalk(1)

0.2

LSB

other channel

ANALOG OUTPUT (VOUT-0 to VOUT-7)

(2)

VREF = +5V

+30

Voltage output(3)

VREF = +1.5V

Output impedance

Code = 8000h

0.5

Ω

Short-circuit current(4)

±10

Load current

See Figure 89 and Figure 90

±3

TA = +25°C, device operating for 500 hours, full-scale output

3.4

ppm of FSR

Output drift vs time

TA = +25°C, device operating for 1000 hours, full-scale output

4.3

ppm of FSR

Capacitive load stability

500

To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0100h to

μs

FFFFh and FFFFh to 0100h

To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0100h to FFFFh

Settling time

μs

and FFFFh to 0100h

To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7F00h to 8100h

μs

and 8100h to 7F00h

Slew rate(5)

μs

Power-on delay(6)

From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low

200

μs

Power-down recovery time

μs

Digital-to-analog glitch(7)

Code from 7FFFh to 8000h and 8000h to 7FFFh

nV-s

Glitch impulse peak amplitude

Code from 7FFFh to 8000h and 8000h to 7FFFh

(1)

The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc

change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With

high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.

(2)

Specified by design.

(3)

The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF) for gain = 6. The maximum value of the analog output must not be

greater than (AVDD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.

(4)

When the output current is greater than the specification, the current is clamped at the specified maximum value.

(5)

Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.

(6)

Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid

digital communication.

(7)

Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as

the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.

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