DAC8728 datasheet(11/52 Pages) TI

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DAC8728

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SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009

PIN DESCRIPTIONS (continued)

PIN NO.

NAME

QFN-56

TQFP-64

I/O

DESCRIPTION

Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the

contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding

LDAC

level simultaneously when the DAC latch is updated. See the DAC Output Update section for details. If

asynchronous mode is desired, LDAC must be permanently tied low before power is applied to the

device. If synchronous mode is desired, LDAC must be logic high during power-on.

Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values defined

RST

by the RSTSEL pin. CS must be at logic high when RST is used.

Address bit A0 to specify the internal registers.

Address bit A1 to specify the internal registers.

DVDD

Digital power supply

DGND

Digital ground

Address bit A2 to specify the internal registers.

Address bit A3 to specify the internal registers.

Address bit A4 to specify the internal registers.

DGND

Digital ground

General-purpose digital input/output. This pin is a bidirectional, open-drain, digital input/output, and

GPIO

I/O

requires an external pullup resistor. See the GPIO Pin section for details.

Output reset selection. Selects the output voltage on the VOUT pin after power-on or hardware reset.

RSTSEL

Refer to the Power-On Reset section for details.

VOUT-7

DAC-7 output

OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation

OFFSET-B

(AVSS = 0V). This pin is not intended to drive an external load.

AVSS

Negative analog power supply. Connect to AGND in single-supply operation.

VOUT-6

DAC-6 output

AGND-B

Group B(2) analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.

AVDD

Positive analog power supply

VOUT-5

DAC-5 output

REF-B

Group B(2) reference input

VOUT-4

DAC-4 output

14, 22, 23,

28, 31, 32,

—

Not connected

35, 45, 53

I/O

Data bit 0

I/O

Data bit 1

I/O

Data bit 2

I/O

Data bit 3

I/O

Data bit 4

I/O

Data bit 5

I/O

Data bit 6

DGND

Digital ground

IOVDD

Digital interface power supply

DVDD

Digital power supply

R/W

Read and write signal. High for reading operation; low for writing operation.

Chip select input (active low)

I/O

Data bit 7

I/O

Data bit 8

I/O

Data bit 9

D10

I/O

Data bit 10

D11

I/O

Data bit 11

D12

I/O

Data bit 12

(2)

Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.

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