IR3521

Page 20

V3.03

Serial VID Interface Protocol and VID-on-the-fly Transition

The IR3521 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which are

based on High-Speed I

SVC and SVD. The SVC pin of the IR3521 does not have an open drain output since AMD SVID protocol does not

support slave clock stretching.

The IR3521 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte

protocol is used by the IR3521 VID-on-the-fly transactions. The IR3521 will wait until it detects a start bit which is

defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow

the start bit. This address code will be compared against an internal address table and the IR3521 will reply with an

acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.

The SVD pin is pulled low by the IR3521 to generate the ACK bit. Table 4 has the list of addresses recognized by

the IR3521.

The processor should then transmit the 8-bit data word immediately following the ACK bit. The first data bit (bit 7),

of the SVID data word, represents the Power State Indicator (PSI) bit which is passed on to the phase ICs via the

IR3521 PSI_L pin. PSI_L is pulled high by an internal 10K resistor to VCCL when data bit 7 of an SVID command

is high. A low, on this bit (bit 7), will pull the PSL_pin low and trigger all connected, predetermine, phase ICs to turn

off. If transitioning from one phase to multiple phases, the last phase IC, or returning phase IC, should be left on to

ensure the fastest possible clock frequency calibration. A shorter calibration time will help minimize droop at the

VDD output when leaving PSI_L mode. The remaining data bits SVID[6:0] select the desired VDACx regulation

voltage as defined in Table 3. The IR3521 replies again with an ACK bit once the data is received. If the received

data is not a VID-OFF command, the IR3521 immediately changes the DAC analog outputs to the new target.

VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example.

Table 1 – 2-bit Boot VID codes

Table 2 – VFIX mode 2 bit VID Codes

SVC

SVD

Output Voltage(V)

0

0

1.1

0

1

1.0

1

0

0.9

1

1

0.8

Figure 12 Send Byte Example

SVC

SVD

Output Voltage(V)

0

0

1.4

0

1

1.2

1

0

1.0

1

1

0.8