IR3521 datasheet(40/45 Pages) IRF

40 / 45 page

IR3521

Page 40

V3.03

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.



Dedicate at least one middle layer for a ground plane LGND.



Connect the ground tab under the control IC to LGND plane through a via.



Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce

the noise coupling.



Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.



Place the following critical components on the same layer as control IC and position them as close as

possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for

the connection.



Place the compensation components on the same layer as control IC and position them as close as possible

to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.



Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.



Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.



Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation

components.

IR3521 Datasheet(PDF) 40 Page - International Rectifier