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IR3521 Datasheet(PDF) 16 Page - International Rectifier |
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IR3521 Datasheet(HTML) 16 Page - International Rectifier |
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16 / 45 page  IR3521 Page 16 V3.03 SVD VCCL- 1.2V VCCLDRV VOUT1 VID OFF 400k SET DOMINANT UV CLEARED FAULT LATCH1 VID3 25k + - S R Q DIS OPEN DAISY IDCHG 4.5uA VOSEN2- VOSEN2+ + - FB2 EAOUT2 VDAC2 OV1 OCSET2 SS/DEL1 IIN2 47uA VCCL VCCL IDCHG1 VID7 + - 3.9V SS/DEL CLEARED FAULT LATCH1 RESET DOMINANT POWER-UP OK LATCH DELAY COMPARATOR SET DOMINANT VIDSEL DISCHARGE COMPARATOR 80mV 120mV IVOSEN- 0.2V DISABLE2 OC1 AFTER VRRDY OV1 FAULT LATCH IROSC OPEN SENSE1 ICHG 50uA Metal to SVID OVER VOLTAGE COMPARATOR VDAC BUFFER AMPLIFIER ERROR AMPLIFIER FLT1 SVID to SVID SVID to Metal Low to High VID3 High to Low DLY OUT1 Vout1 VID On-The-Fly High to Low VDAC2 VOUT2 VID OFF DLY OUT2 UV2 SVID ENABLED DVID2 VID3 VID3 Connection to VCCL VOUT1 UV COMPARATOR UV2 275mV 315mV VOUT2 UV COMPARATOR UV1 SSCL FS2 VDAC1 SVID to SVID REMOTE SENSE AMPLIFIER DLY OUT1 1.6V 50mV ISINK ISOURCE IVOSEN2- IVOSEN2+ 200mV 0.4V DYNAMIC VID2 DOWN DETECT COMPARATOR VCCL*0.9 1.4V SOFT START CLAMP 260mV OC LIMIT COMPARATOR SSCL FS1 FLT2 VCCL RESET OPEN SENSE LINE2 4 OPEN SENSE LINE DETECT COMPARATORS 60mV 1.08V IOCSET VDAC1 VID3 IROSC OV1_2 + - S R Q 47uA IDCHG2 SSCL FS1 + - OPEN CONTROL2 S R Q Q U? AND2 25k DIS VCCL + - + - DIS 275mV 315mV SVID to Metal VID3 25k UV CLEARED FAULT LATCH2 SET DOMINANT + - VCCL 25k S R Q S R Q READ & STORE PRE-PWROK 2 BIT VID SSCL FS2 DIS PHSOUT FLT1 DYNAMIC VID1 DOWN DETECT COMPARATOR 8 Pulse Delay VID3 FLT2 IROSC OPEN DAISY OPEN CONTROL LOOP COMPARATOR PHSOUT DLY OUT1 OVLATCH 4.5uA DIS IDCHG VFIX Mode OC2 Bf VRRDY DISABLE VRRDY OVLATCH VCCL UVLO PHSOUT CLKOUT EPAD ROSC PHSIN FAULT PHSIN IROSC PHSOUT CLKOUT VID0 ROSC BUFFER AMPLIFIER CURRENT SOURCE GENERATOR OC1 Bf VRRDY OPEN DAISY CHAIN 0.6V EN EN DETECTION PULSE2 DIS OC DELAY COUTER IROSC OV2 OV1 reset reset DIS DIS PHSOUT IROSC DIS DIS OC DELAY COUTER DIS PHSOUT OV2 VCCL DLY OUT2 VRRDY OVLATCH 10k PSI_L DCHG2 DLY OUT2 S R Q Q SVI (Seriel VID Interface) 0.86 SVC DCHG1 FLT1 DCHG1 SVD VCCL DIS VOUT2 DISABLE VCCL UVLO VCCL UVLO DETECTION PULSE1 OV1-2 OV1 Metal to SVID OV2 25k + - SS/DEL2 Back to PRE-PWROK 2 BIT VID + - PGOOD + - VCCLDRV VCCLFB VCCL ENABLE VOSEN1- VOSEN1+ VOUT1 VDRP1 IIN1 OCSET1 FB1 EAOUT1 VDAC1 VID3 VCCL VCCL FLT2 VID3 VID7 IVOSEN- VIDSEL UV1 IROSC DISABLE1 PWROK IROSC DELAY COMPARATOR SET DOMINANT 3.9V SS/DEL CLEARED FAULT LATCH2 VDD ERROR AMPLIFIER 1.65V 1V ENABLE COMPARATOR VDAC BUFFER AMPLIFIER D/A CONVERTER OVER VOLTAGE COMPARATOR 250nS BLANKING Vout2 VID On-The-Fly High to Low VCCL REGULATOR AMPLIFIER VDRP AMPLIFIER 0.94 1.2V VCCL UVL COMPARATOR ISINK ISOURCE REMOTE SENSE AMPLIFIER DIS DISCHARGE COMPARATOR 80mV 120mV RESET DOMINANT POWER-UP OK LATCH IVOSEN1+ 200mV 1.6V 50mV 0.2V 0.4V VCCL*0.9 IVOSEN1- SOFT START CLAMP IFB SET DOMINANT OC LIMIT COMPARATOR 1.4V FLT2 4 OPEN SENSE LINE DETECT COMPARATORS 60mV 260mV OV FAULT LATCH DIS 50uA OPEN SENSE LINE1 OC2 AFTER VRRDY IOCSET ICHG VDAC2 EN 1.08V VCCL RESET 8 Pulse Delay DETECTION PULSE1 EN INTERNAL CIRCUIT BIAS + - U? AND2 25k DCHG2 + - OPEN SENSE2 VCCL UVLO 25k FLT1 + - 25k OPEN CONTROL LOOP COMPARATOR VCCL VID3 S R Q OPEN CONTROL1 DETECTION PULSE2 SVC SELECT MODE CLOCK MEMORY SELECT MODE DISABLE D . Q Q DISABLE POR SELECT MODE VDD VCCL-UVLO Figure 8 Block Diagram |
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