IR3521 datasheet(23/45 Pages) IRF

23 / 45 page

IR3521

Page 23

V3.03

Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz

VCCL Under Voltage Lockout (UVLO)

The IR3521 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply

voltage since this voltage is used for the gate drive. As VCC begins to rise during power up, the VCCLDRV pin will

be high impedance therefore allowing VCCL to roughly follow VCC-NPNVBE until VCCL is above 94% of the voltage

set by resistor divider at VCCLFB pin. At this point, the OVX and UV CLEARED fault latches will be released. If

VCCL voltage drops below 86% of the set value, the SS/DEL CLEARED fault latch will be set.

VID OFF Codes

SVID OFF codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down EAOUTX

voltage and discharging SS/DELX through the 50uA discharge current, but do not drive PGOOD low. Upon receipt

of a non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in

Figure 10.

Power Good (PGOOD)

The PGOOD pin is an open-collector output and should have an external pull-up resistor. During soft start, PGOOD

remains low until the output voltage is in regulation and SS/DELX is above 3.9V. The PGOOD pin becomes low if

ENABLE is low, VCCL is below 86% of target, an over current condition occurs for at least 1024 PHSOUT clocks

prior to PGOOD, an over current condition occurs after PGOOD and SS/DELX discharges to the delay threshold, an

open phase timing daisy chain condition occurs, VOSNS lines are detected open, VOUTX is 315mV below VDACX,

or if the error amp is sensed as operating open loop for 8 PHSOUT cycles. A high level at the PGOOD pin indicates

that the converter is in operation with no fault and ensures the output voltage is within the regulation.

PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but

the VR continues to regulate its output voltages. The PWROK input may or may not de-assert prior to the voltage

planes falling out of specification. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage.

VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code

and a voltage associated with another VID code is not considered to be out of specification.

A PWROK de-assert while ENABLE is high results in all planes regulating to the previously stored 2-bit Boot VID. If

the 2-bit Boot VID is higher than the VID prior to PWROK de-assertion, this transition will NOT be treated as VID on-

the-fly and if either of the two outputs is out of spec high, PGOOD will be pulled down.

IR3521 Datasheet(PDF) 23 Page - International Rectifier