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DLPC200 Datasheet(PDF) 12 Page - Texas Instruments |
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DLPC200 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 41 page  DLPC200 DLPS014A – APRIL 2010 – REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL FUNCTIONS (continued) TERMINAL I/O CLOCK DESCRIPTION TYPE(1) SYSTEM NAME NO. FLASH_SRAM_OE C10 O3 Flash output enable FLASH_SRAM_RDY C13 I3 Flash wait FLASH_SRAM_RST C12 O3 Flash reset FLASH_SRAM_WE A6 O3 Flash write enable SRAM_CE B11 O3 SRAM chip enable SRAM_LB D9 O3 SRAM lower byte enable SRAM_UB C9 O3 SRAM upper byte enable SDRAM Interface MEM_CLK_P0 R2 O5 DDR2 memory, differential memory clock MEM_CLK_N0 R1 O5 DDR2 memory, differential memory clock MEM_CLK_P1 U3 O5 DDR2 memory, differential memory clock MEM_CLK_N1 U4 O5 DDR2 memory, differential memory clock MEM_CLK_P2 AC5 O5 DDR2 memory, differential memory clock MEM_CLK_N2 AC4 O5 DDR2 memory, differential memory clock MEM_CLK_P3 AE14 O5 DDR2 memory, differential memory clock MEM_CLK_N3 AF14 O5 DDR2 memory, differential memory clock MEM_CKE0 AF12 O5 MEM_BA0 Y19 O5 MEM_CLK MEM_BA1 AD21 O5 MEM_CLK MEM_BA2 AE7 O5 MEM_CLK MEM_A0 AD24 MEM_A1 AF21 MEM_A2 AG23 MEM_A3 AE8 MEM_A4 AG12 MEM_A5 AF23 MEM_A6 AC17 DDR2 memory, Multiplexed Row and Column Address. The memory MEM_A7 AA16 in the kit is 512 Mbit in a x16 mode, 8 Meg x 16 bits x 4 banks. Only O5 MEM_CLK A(12:0) and BA(1:0) are currently used. A(15:13) and BA(2) are MEM_A8 AE23 reserved for future use (RFU). MEM_A9 AE22 MEM_A10 AE16 MEM_A11 AD25 MEM_A12 AF19 MEM_A13 AH10 MEM_A14 AA8 MEM_A15 AD11 MEM_CAS AG19 O5 MEM_CLK Column address strobe. Active low. MEM_RAS AE20 O5 MEM_CLK Row address strobe. Active low. MEM_CS0 AF13 O5 MEM_CLK Chip select. Active low. MEM_WE AG25 O5 MEM_CLK Write enable. Active low. MEM_ODT AH12 O5 MEM_CLK MEM_DM0 W2 O5 MEM_CLK MEM_DM1 AE2 O5 MEM_CLK MEM_DM2 AH6 O5 MEM_CLK MEM_DM3 AF7 O5 MEM_CLK 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPC200 |
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