DLPC200 datasheet(31/41 Pages) TI

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ADDRESS

READ CYCLE

WRITE CYCLE

DATA_OUT

DATA

ADDRESS

OHA

SCE

PWE

DLPC200

www.ti.com

DLPS014A – APRIL 2010 – REVISED MAY 2010

Figure 12. SRAM Interface Timing

Recomended Serial Flash Devices shows the Serial Flash parts that were tested by TI and found to work

properly with the DLPC200.

Recommended Static RAM Devices

PART NUMBER

MANUFACTURER

SIZE

CY7C1011DV33

Cypress

2 Mbit

DMD Interface

The DLPC200 ASIC DMD interface consists of a 200 MHz (nominal) DDR output-only interface with LVDS

signaling.

DMD INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

TYP

MAX

UNIT

fclock

Clock frequency, DCLK_A & DCLK_B

200

MHz

tp_clkper

Clock period, DCLK_A & DCLK_B

5.0

tp_wh

Pulse width low, DCLK_A & DCLK_B

1.25

tp_wl

Pulse width high, DCLK_A & DCLK_B

1.25

tskew

Channel B relative to channel A

-1.25

1.25

Output setup time – D_A(0:15) & D_B(0:15) relative to both rising and falling edges

0.35

tp_su

of DCLK_A & DCLK_B, respectively

Output hold time – D_A(0:15) & D_B(0:15) relative to both rising and falling edges

0.35

tp_h

of DCLK_A & DCLK_B, respectively

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