DLPC200

DLPS014A – APRIL 2010 – REVISED MAY 2010

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DLPC200 Master, I

programming (continued)

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input

is high, is sent by the master.

Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period. Setup and

hold times must be met to ensure proper operation.

I

PARAMETER

MIN

MAX

UNIT

0

400

kHz

1

ms

1

ms

20

ns

100

ns

100

ns

100

ns

50 pF

30

200

ns

1.3

ms

1

ms

1

ms

1

ms

Valid-data time

SCL low to SDA output valid

1

ms

Valid-data time of ACK condition

ACK signal from SCL low to SDA (out) low

1

ms

0

100

pF

22

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