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DLPC200 Datasheet(PDF) 15 Page - Texas Instruments |
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DLPC200 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 41 page  DLPC200 www.ti.com DLPS014A – APRIL 2010 – REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL FUNCTIONS (continued) TERMINAL I/O CLOCK DESCRIPTION TYPE(1) SYSTEM NAME NO. LED_SUBFRAME E26 O3 Async Subframe signal used by LED Driver. Controlled by programmable DMD Sequence Timing (Active High) SYNC_0 F26 O3 Async Extra Strobe. Controlled by programmable DMD Sequence Timing (Active High) SYNC_1 F25 O3 Async Extra Strobe. Controlled by programmable DMD Sequence Timing (Active High) SYNC_2 F24 O3 Async Extra Strobe. Controlled by programmable DMD Sequence Timing (Active High) LED_EN L28 O3 Async LED Driver Enable. Active low output control to external LED Drive Logic. LED_SYNC M21 O3 Async Reserved for future use; weak pull-up applied LED_SYNCEN C24 O3 Async Inverted LED_LIT signal LED_LIT J28 I3 Async LED Driver Status LED_SENS K27 I3 Async Reserved for future use. LED_SPI_CLK N26 O3 Async LED SPI MASTER CLOCK LED_SPI_CS M26 O3 LED_SPI_CLK LED SPI MASTER Chip Select LED_SPI_DIR P25 O3 LED_SPI_CLK LED SPI MASTER Driver Direction LED_SPI_MISO L27 I3 LED_SPI_CLK LED SPI MASTER Data IN LED_SPI_MOSI L26 O3 LED_SPI_CLK LED SPI MASTER Data OUT; weak pull-up applied System Interfaces CFG_CSO Chip Select Output for an external serial configuration device. Active E2 O3 CFG_DCLK low. CFG_CLK P3 O3 CFG_DCLK Configuration Serial EPROM data clock. CFG_ASDI Data input from an external serial configuration device. Provides N7 I3 CFG_DCLK configuration data for the device. CFG_ASDO Serial Data Output. This pin sends address and control information to F4 O3 CFG_DCLK the external PROM during configuration. CFG_STATUS M6 O3 CFG_DCLK Configuration status pin. CFG_DONE Configuration Done status pin. Signal goes high at the end of P24 O3 CFG_DCLK configuration. CFG_MSEL0 N22 Configuration Mode Selection signals. CFG_MSEL1 P23 I3 Async CFG_MSEL2 M22 CFG_MSEL3 P22 CFG_CE R8 I3 Async Chip Enable. Active low. CFG_EN Configuration control. Configuration will start when a low to high P4 I3 Async transition is detected at this pin. CFG_CEO P28 O1 Async REF_CLK J27 I3 50 MHz reference clock, 3.3V RESET A14 I3 Async Device reset (active low) PWR_GOOD A23 I3 Async System power good indicator RSVD_H10 N4 B2 GPIO RSVD_H11 L2 B2 GPIO RSVD_H12 K4 B2 GPIO RSVD_H6 G1 B2 GPIO RSVD_H5 G5 B2 GPIO RSVD_H4 G6 B2 GPIO RSVD_H2 E1 B2 GPIO Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): DLPC200 |
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