24-Bit Input Bus, RGB888

PORTx_D(23:0) of the Input Pixel Data Bus

Default Bus Assignment Mapping

RGB888 Format

B4

B3

B2

B1

B0

G2

G1

G0

B7

B6

B5

G7

G6

G5

G4

G3

R4

R3

R2

R1

R0

R7

R6

R5

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

20

19

18

17

16

23

22

21

DLPC200

DLPS014A – APRIL 2010 – REVISED MAY 2010

www.ti.com

Video Input Pixel Interface

Figure 2 illustrates how pixels should be mapped to the input data bus for both port 1 and port 2.

Figure 2. Pixel Mapping

IMAGE SYNC AND BLANKING REQUIREMENTS

PARAMETER

MIN

MAX

UNIT

Vertical Sync Width

1

clocks

Vertical Back Porch

14

lines

Vertical Front Porch

2

lines

Horizontal Sync Width

1

clocks

Horizontal Back Porch

64

clocks

Horizontal Front Porch

75

clocks

TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Clock frequency, PORTx_CLK

80

MHz

Pulse duration, high

45% to 55% reference points (signal)

5.6

ns

Pulse duration, low

45% to 55% reference points (signal)

5.6

ns

Setup time, PORTx_D(23-0) valid before

1.5

ns

PORTx_CLK

Hold time, PORTx_D(23-0) valid after

1.5

ns

PORTx_CLK

Setup time, PORTx_VSYNC valid before

1.5

ns

PORTx_CLK

Hold time, PORTx_VSYNC valid after

1.5

ns

PORTx_CLK

Setup time, PORTx_HSYNC valid before

1.5

ns

PORTx_CLK

Hold time, PORTx_HSYNC valid after

1.5

ns

PORTx_CLK

Setup time, PORTx_IVALID valid before

1.5

ns

PORTx_CLK

Hold time, PORTx_IVALID valid after

1.5

ns

PORTx_CLK

(1)

PCLK may be inverted from that shown in Figure 3. In that case the same specifications in the table are valid except now referenced to

the falling edge of the clock. If the falling edge of PCLK is to be used, an USB or SPI command is needed to tell the DLPC200 to use

the falling edge of PCLK.

20

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